1. Field of the Invention
The invention relates to a device for coding digital signals corresponding to television images having a given definition, comprising:
(A) a stage for selecting the coding mode of signals to be coded from current input signals to the coding device on the one hand and from predicted signals on the other hand, based on the preceding input signals of the device, said stage supplying the signals to be coded and coding mode information; PA1 (B) a coding stage; PA1 (C) an image reconstruction stage in a first path for reconstructing the image in accordance with said given definition; PA1 (D) a stage for estimating the motion between images, supplying motion information; PA1 (E) a stage for predicting from output signals of said image reconstruction and/ motion estimation stages the output signals of said prediction stage constituting said predicted signals transmitted to said coding mode selection stage. PA1 (a) a stage for selecting the coding mode of the signals to be coded from current input signals of said coding device on the one hand and from predicted signals on the other hand, based on the preceding input signals of said device, said preceding and current input signals being considered as blocks of a given size representing a subdivision of images and being treated independently; PA1 (b) a coding stage; PA1 (c) an images reconstruction stage for reconstructing the image in accordance with said given definition on the one hand and in accordance with a reduced definition on the other hand; PA1 (d) a stage for estimating the motion between images; and supplying motion information; PA1 (e) for supplying said predicted signals, a stage for predicting from the output signals of said motion estimation and image reconstruction stages the information components which are additional and relative to the estimated motion between images and to the selected coding mode being intended, like the coded signals, for transmission and/or storage. PA1 (a) an inverse quantizing circuit; PA1 (b) an inverse scanning conversion circuit; PA1 (c) an inverse orthogonal transform stage; PA1 (d) a circuit for reconstructing the signal in accordance with said given definition, as would be decoded after transmission, but for transmission errors; characterized in that in said image reconstruction stage the second reconstruction path comprises: PA1 (a) said inverse quantizing circuit; PA1 (b) said inverse scanning conversion circuit; PA1 (c) a clipper circuit for taking a given fraction of the signals at the output of said inverse quantizing circuit; PA1 (d) an inverse orthogonal transform circuit; PA1 (e) a circuit for reconstructing the signal having a reduced definition as would be decoded after transmission, but for transmission errors; PA1 (f) a memory for storing said reconstructed signal; (g) a motion compensation circuit between the output of said memory and said circuit for reconstructing the reduced definition signal; PA1 (h) a multiplier for multiplying the output signal of the first reconstruction path by a coefficient .alpha. between 0 and 1; PA1 (i) a multiplier for multiplying the output signal of the second reconstruction path by the coefficient (1-.alpha.), a phase restoring and resampling circuit being arranged between said output of the second reconstruction path and the corresponding input of the associated multiplier; PA1 (j) an adder for adding the output signals of said multipliers; PA1 (k) a weighting memory for storing the output signal of said adder; PA1 (l) a prediction circuit for receiving the output signal of said weighting memory and the motion information components supplied by said motion estimation stage. PA1 (a) an orthogonal transform stage for said input current signals; PA1 (b) an inter/intradecision circuit for also receiving said predicted signals; and in which first reconstruction path comprises a series arrangement of: PA1 (c) an inverse quantizing circuit; PA1 (d) a circuit for reconstituting the block in accordance with said given definition; PA1 (e) an inverse orthogonal transform stage; PA1 (f) a memory for the information components of said given definition; characterized in that in said reconstruction stage the second reconstruction path comprises: PA1 (a) said inverse quantizing circuit; PA1 (b) a clipper circuit for taking a given fraction of the signals present at the output of said inverse quantizing circuit; PA1 (c) a circuit for reconstituting the block in accordance with said reduced definition; PA1 (d) an inverse orthogonal transform stage; PA1 (e) a memory for the information components of said reduced definition; and in that the image reconstitution circuit comprises: PA1 (f) at the output of said first path, a first reconstitution branch comprising a first prediction circuit with motion compensation, a first orthogonal transform circuit and a low-frequency clipper circuit for eliminating, in the coefficients resulting from said orthogonal transform, a given fraction representing the coefficients of the lowest frequency; PA1 (g) at the output of the second path, a second reconstitution branch comprising a second prediction circuit with motion compensation and a second orthogonal transform circuit; PA1 (h) a circuit for combining the output signals of said first and second branches for supplying said predicted signals transmitted to said coding mode selection stage. PA1 (a) a multiplier for multiplying the output signal of the first branch by a coefficient .alpha. between 0 and 1, which signal corresponds to said coefficients eliminated by the low-frequency clipper circuit; PA1 (b) a multiplier for multiplying the output signal of said second branch by the coefficient (1-.alpha.); PA1 (c) an adder for adding the output signals of said multipliers, the output signal of said adder being applied to the corresponding input of the combination circuit. PA1 (A) a stage for reconstructing the image in accordance with said reduced definition from the decoded signals; PA1 (B) a stage for motion compensation based on said additional information components; PA1 (C) a stage for prediction based on the output signals of said image reconstruction stage. PA1 (A) the stage for reconstructing the image in accordance with said reduced definition comprises a series arrangement of: PA1 (a) a clipper circuit for taking a given fraction of the signals after decoding; PA1 (b) an inverse orthogonal transform circuit; PA1 (c) an adder whose first input receives the output signal of said inverse orthogonal transform circuit; PA1 (d) a memory for storing the image reconstituted in accordance with the reduced definition and being present at the output of said adder; PA1 (e) a first circuit for compensating motion, receiving the output signal of said memory and the motion information components, and having its output connected to the second input of said adder; PA1 (B) the prediction stage comprises: PA1 (f) a first multiplier for multiplying the output signals of said decoding device by a coefficient .alpha. between 0 and 1; PA1 (g) a second multiplier for multiplying the output signal of said stage for reconstructing the image in accordance with said reduced definition by the coefficient (1-.alpha.), a phase restoring and resampling circuit being arranged between said output and the corresponding input of said second multiplier; PA1 (h) an adder for adding the output signals of said first and second multipliers; PA1 (i) a memory for weighted mixing of images in accordance with said given definition and in accordance with said reduced definition; PA1 (C) the motion compensation stage comprises: PA1 (j) a second motion compensation circuit receiving the output signal of said prediction stage and the additional motion and coding mode information components; PA1 (k) an adder for adding the output signals of said decoding chain and said second motion compensation circuit. PA1 (A) the stage for reconstructing the image in accordance with said reduced definition comprises a series arrangement of: PA1 (a) a clipper circuit for taking a given fraction of the signals after decoding; PA1 (b) a circuit for reconstituting the block in accordance with said reduced definition; PA1 (c) an inverse orthogonal transform circuit; PA1 (d) a second memory for storing information components in accordance with said reduced definition; PA1 (B) the motion compensation stage comprises first and second motion compensation circuits each receiving the output signal of one of said two memories for storing information components and for storing the coding mode and motion information components; PA1 (C) the prediction stage comprises: PA1 (f) at the output of that one of said motion compensation circuits which follows said memory for storing the information components in accordance with the given definition, a first reconstitution branch comprising a first orthogonal transform circuit and a low-frequency clipper circuit for eliminating, in the coefficients resulting from said orthogonal transform, a given fraction representing the coefficients of the lowest frequency; PA1 (g) at the output of the other one of said motion compensation circuits which follows said memory for storing the information components in accordance with the reduced definition, a second reconstitution branch comprising a second orthogonal transform circuit; PA1 (h) at the output of said first and second parallel branches a circuit for combining the output signals of said first and second branches; PA1 (i) an adder for adding the output signals of said combination circuit and of the inverse quantizing circuit of the variable length decoding chain, arranged between said inverse quantizing circuit and the inverse orthogonal transform circuit following the last-mentioned circuit. PA1 (a) a multiplier for multiplying the output signal of said first branch by a coefficient .alpha. between 0 and 1, which signal corresponds to said coefficients eliminated by the low-frequency clipper circuit; PA1 (b) a multiplier for multiplying the output signal of said second branch by the coefficient (1-.alpha.); PA1 (c) an adder for adding the output signals of said multipliers, the output signal of said adder being applied to said corresponding input of the combination circuit.
The invention also relates to a device for decoding coded digital signals which have been transmitted and/or stored after processing in a device for coding digital signals corresponding to television images of a given definition, said coding device comprising:
This invention can be used to advantage in the field of television picture reception in accordance with two definition levels for ensuring the restitution of high-definition images of excellent quality which can nevertheless be received by conventional television receivers having a lower definition.
2. Description of the Related Art
The transmission of high-definition digital television images is currently the subject of intensive research. However, the industries concerned have realised at a very early stage that this novel service would only be successful if the high-definition programs could be received not only by high-definition television receivers but by conventional receivers as well.
Such a transmission, which is referred to as "compatible", is effectively ensured if a fraction of the multitude of data corresponding to the high-definition program can easily be taken and used for the conventional receiver to supply the normal television images (compatible images: 625 lines, 50 Hz, 2:1, 16/9 frame). This technical solution provides the possibility of simultaneously transmitting conventional television programs and high-definition television programs with a certain economy of information output (the output thus economized is substantially that which would correspond to the transmission of high definition TV images alone).
The separation of the multitude of high-definition data into two parts one corresponding to mutually compatible data (which will hereinafter be referred to as TV information components), and to the other to complementary additional data (relating only to the high-definition images and hereinafter referred to as HD or HDTV information components), constitutes a drawback at the level of the high-definition coder (or HD coder) upon transmission, because the entire multitude of data must comprise the information components from which compatible images can be subsequently reconstructed. The positioning of these two information components may particularly lead to a degradation of the high-definition image quality.
Therefore, the solution which currently seems to be the best to ensure compatible transmission is based on the use of a coder employing an orthogonal transform such as a discrete cosine transform (DCT) which acts on data blocks into which each image is divided. The reconstruction of the compatible images based on high-definition data is realised by means of a cut-off in the frequency domain: for each high-definition image block to which the orthogonal transform is applied only those coefficients resulting from this transform which correspond to the lowest frequencies are transmitted to the compatible image decoder (or TV decoder). The coefficients thus selected become the constituent coefficients of new image blocks having dimensions which in this case are twice smaller than those of the original blocks in each horizontal and vertical direction.
The compatible images thus obtained have satisfactory quality as long as the TV decoders do not incorporate motion compensation devices. When such devices are provided, a prediction before the motion is necessary, which may be effected with the high-definition resolution for maintaining the image quality during decoding of the high-definition images. Some disagreement is found between the contents of the image blocks thus predicted during coding and high-definition decoding and the image blocks predicted during decoding of compatible images. Effects which degrade the quality of the compatible images are then produced, which effects are cumulative because of the recursivity of the device.